|本期目录/Table of Contents|

[1]邹连英.单周期8位微控制器的时序及流水线设计[J].武汉工程大学学报,2008,(04):103-107.
 ZOU Lian ying.Timing and pipeline technology of a novelsinglecycle 8bit microcontroller[J].Journal of Wuhan Institute of Technology,2008,(04):103-107.
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单周期8位微控制器的时序及流水线设计(/HTML)
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《武汉工程大学学报》[ISSN:1674-2869/CN:42-1779/TQ]

卷:
期数:
2008年04期
页码:
103-107
栏目:
机电与信息工程
出版日期:
2008-04-30

文章信息/Info

Title:
Timing and pipeline technology of a novel
singlecycle 8bit microcontroller
文章编号:
16742869(2008)04010305
作者:
邹连英
武汉工程大学电气信息学院,湖北 武汉 430074
Author(s):
ZOU Lianying
School of Electrical and Information Engineering,Wuhan Institute of Technology,Wuhan 430074,China
关键词:
微控制器单周期流水线 并行技术
Keywords:
microcontroller one cycle pipeline parallel technology
分类号:
TN 492
DOI:
-
文献标志码:
A
摘要:
分析传统8051微控制器的时序设计可以发现,在12个时钟周期的机器周期架构中存在着巨大的浪费,多数指令被强制去执行哑周期.利用并行技术及流水线技术设计了一个全新的单周期8位微控制器,并详细设计了单周期实现时序及两级流水线技术,最后与传统8位微控制器进行了计算性能对比,可以看出其执行速度比标准8051平均提高10倍左右.
Abstract:
By analyzing the characteristic of traditional 8051 microcontroller, we found that there are great time wastes on twelve cycle architecture. In order to improve the 8bit microcontrollers performance, we design and implement a onecycle 8bit microcontroller, using parallel technology and pipeline technology. This paper described the time sequence of one cycle architecture and its two stage pipeline technology in detail. Compared with traditional 8bit microcontroller, the new one cycle architectures speed of operation is about ten times more than traditional 8bit architecture.

参考文献/References:

[1]冯博琴.微型计算机原理与接口技术[M]. 北京:清华大学出版社,2002:3045.
[2]李丽,高明伦,张多利,等. 8位RISC微控制器IP软核的设计[J]. 微电子学与计算机,2001,(18): 1014.
[3]Gschwind M, Salapura V, Maurer D. FPGA prototyping of a RISC processor core for embedded applications[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2001, 9(2): 241250.
[4]Sweetman D. MIPS处理器设计透视[M]. 赵俊良译. 北京:北京航空航天大学出版社,2005:213256.
[5]Clark L T, Hoffman E J, Miller J, et al. An embedded 32b microprocessor core for lowpower and highperformance applications[J]. IEEE Journal of SolidState Circuits, 2001, 36(11): 15991608.

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备注/Memo

备注/Memo:
收稿日期:20070522
作者简介:邹连英(1977),女,湖北黄冈人,讲师,博士.
研究方向:VLSI集成电路设计、嵌入式系统设计.
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